High-sample rate, high-linearity DACs are commonly employed in state-of-the art radio frequency (RF) radio transmit paths to convert base-band and intermediate-frequency (IF) data from the digital to analog domains. In some cases, these signals are then fed into an up-conversion mixer where they are translated to a higher RF frequency. In other cases, more advanced DACs have been used to output the RF signal directly at very high sample rates (>4 Gsps). Regardless of the particular system architecture, a common feature of these DACs is that they support a very wide output bandwidth typically on the order of >300 MHz, and must maintain high-linearity with a fairly low noise floor.
Since these demanding applications tend to require high-resolution (>14 bits), the size and complexity of these DACs are also quite high. One way to reduce the number of physical bits required is to use a delta-sigma modulator and over-sampling. This process is summarized in FIG. 1.
FIG. 1 illustrates a known oversampled digital to analog converter. This example illustrates the case where the data is over-sampled by a factor of 2×. The input data is sampled at a rate fs, and is Ndata bits wide. In a typical known system, Ndata>14 bits and fs>600 Msps. This digital data stream is then up-sampled (increased in sample rate) at an up-sampler 10 by the over-sample factor to 2*fs. After low-pass filtering in a low-pass filter 12, this data is then passed through a delta-sigma modulator (DSM) 14 which truncates Ndata to a lower number of bits Ndsm. The result of this truncation would normally increase the noise-floor of the data; however, the delta-sigma modulator is specifically designed to take this extra noise and move it to higher frequencies out-of-band as shown in dashed lines in areas (d), (e) and (f) of FIG. 1.
The main advantage here is that the high-resolution input data is now effectively compressed into a lower number of physical bits, which allows for a simpler design of the analog DAC 16. For example, normally an Ndata=16-bit data signal would require an analog DAC that can synthesize ˜216 unique levels. In the case of a delta-sigma architecture where this is compressed to Ndsm=10-bits, the physical DAC can represent the same signal, without any loss of information, using only 210 levels. This represents a reduction in complexity of ˜64×. Note, however, that the cost is that the data-rate is now 2× faster. After being converted into the analog domain, the signal is then filtered by an anti-aliasing low-pass filter 18 to re-construct the digital signal.
High-performance DACs that target applications with stringent linearity and noise requirements, along with wide signal bandwidths, typically have large power consumption and require significant area. One way to achieve the high-bandwidth and resolution is to use an over-sampled architecture. As described in relation to FIG. 1, instead of implementing a full N-bit DAC equal to the input data bus width, a delta-sigma modulator is employed to reduce the number of unique analog levels that the DAC needs to represent. Noise-shaping by the delta-sigma modulator suppresses the added quantization noise.
A drawback of the architecture of FIG. 1 is that the digital circuitry must operate at the over-sampled data rate. For example, if the required signal bandwidth is 300 MHz, and a 2× over-sampled architecture is desired, the DSM, DAC and all associated custom high-speed digital circuitry must run at >1.2 Gsps. Also, due to the large size and high-switching frequencies of these DACs, supply induced-noise can be a large source of spurious emissions and non-linearity in integrated radio systems.
It is desirable to provide a DAC architecture that eases at least one of these implementation difficulties while addressing the need for low spurious emissions and high-linearity.